// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  hipciec_global_reg_reg_offset_field.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  xxx
// Version       :  1.0
// Date          :  2017/10/24
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V4.2 
// History       :  xxx 2018/03/16 18:03:13 Create file
// ******************************************************************************

#ifndef __HIPCIEC_GLOBAL_REG_REG_OFFSET_FIELD_H__
#define __HIPCIEC_GLOBAL_REG_REG_OFFSET_FIELD_H__

#define HIPCIEC_GLOBAL_REG_PORT_CTRL_SFT_RST_LEN    16
#define HIPCIEC_GLOBAL_REG_PORT_CTRL_SFT_RST_OFFSET 16
#define HIPCIEC_GLOBAL_REG_PORT_SFT_RST_LEN         16
#define HIPCIEC_GLOBAL_REG_PORT_SFT_RST_OFFSET      0

#define HIPCIEC_GLOBAL_REG_PORT_EN_LEN    16
#define HIPCIEC_GLOBAL_REG_PORT_EN_OFFSET 0

#define HIPCIEC_GLOBAL_REG_LINKDOWN_CLR_PORT_EN_LEN    16
#define HIPCIEC_GLOBAL_REG_LINKDOWN_CLR_PORT_EN_OFFSET 16
#define HIPCIEC_GLOBAL_REG_PORT_STICKY_SFT_RST_LEN     16
#define HIPCIEC_GLOBAL_REG_PORT_STICKY_SFT_RST_OFFSET  0

#define HIPCIEC_GLOBAL_REG_LINKDOWN_RST_EN_LEN     16
#define HIPCIEC_GLOBAL_REG_LINKDOWN_RST_EN_OFFSET  16
#define HIPCIEC_GLOBAL_REG_LINKDOWN_RST_NUM_LEN    16
#define HIPCIEC_GLOBAL_REG_LINKDOWN_RST_NUM_OFFSET 0

#define HIPCIEC_GLOBAL_REG_TURBO_SIM_LEN    1
#define HIPCIEC_GLOBAL_REG_TURBO_SIM_OFFSET 0

#define HIPCIEC_GLOBAL_REG_LOCAL_LOOPBACK_MODE_LEN    16
#define HIPCIEC_GLOBAL_REG_LOCAL_LOOPBACK_MODE_OFFSET 0

#define HIPCIEC_GLOBAL_REG_MEM_POWER_MODE_LEN    6
#define HIPCIEC_GLOBAL_REG_MEM_POWER_MODE_OFFSET 16
#define HIPCIEC_GLOBAL_REG_TP_RAM_TMOD_LEN       8
#define HIPCIEC_GLOBAL_REG_TP_RAM_TMOD_OFFSET    8
#define HIPCIEC_GLOBAL_REG_SP_RAM_TMOD_LEN       7
#define HIPCIEC_GLOBAL_REG_SP_RAM_TMOD_OFFSET    0

#define HIPCIEC_GLOBAL_REG_TP_RAM_TMOD1_LEN    8
#define HIPCIEC_GLOBAL_REG_TP_RAM_TMOD1_OFFSET 0

#define HIPCIEC_GLOBAL_REG_CFG_PF_VF_SEL_LEN    1
#define HIPCIEC_GLOBAL_REG_CFG_PF_VF_SEL_OFFSET 8
#define HIPCIEC_GLOBAL_REG_CFG_FUNC_SEL_LEN     8
#define HIPCIEC_GLOBAL_REG_CFG_FUNC_SEL_OFFSET  0

#define HIPCIEC_GLOBAL_REG_SKP_DATA_PARITY_ERR_INJECT_EN_LEN    16
#define HIPCIEC_GLOBAL_REG_SKP_DATA_PARITY_ERR_INJECT_EN_OFFSET 0

#define HIPCIEC_GLOBAL_REG_PCIEC_MODE_SEL_LEN    16
#define HIPCIEC_GLOBAL_REG_PCIEC_MODE_SEL_OFFSET 0

#define HIPCIEC_GLOBAL_REG_PORT_INT_RO_0_7_LEN    24
#define HIPCIEC_GLOBAL_REG_PORT_INT_RO_0_7_OFFSET 0

#define HIPCIEC_GLOBAL_REG_PORT_INT_RO_8_15_LEN    24
#define HIPCIEC_GLOBAL_REG_PORT_INT_RO_8_15_OFFSET 0

#define HIPCIEC_GLOBAL_REG_PCIE_RELEASE_DATE_LEN    32
#define HIPCIEC_GLOBAL_REG_PCIE_RELEASE_DATE_OFFSET 0

#define HIPCIEC_GLOBAL_REG_PCIE_VERSION_LEN    32
#define HIPCIEC_GLOBAL_REG_PCIE_VERSION_OFFSET 0

#define HIPCIEC_GLOBAL_REG_CORE_INT_SET_LEN    12
#define HIPCIEC_GLOBAL_REG_CORE_INT_SET_OFFSET 0

#define HIPCIEC_GLOBAL_REG_CORE_INT_MASK_LEN    12
#define HIPCIEC_GLOBAL_REG_CORE_INT_MASK_OFFSET 0

#define HIPCIEC_GLOBAL_REG_CORE_INT_RO_LEN    12
#define HIPCIEC_GLOBAL_REG_CORE_INT_RO_OFFSET 0

#define HIPCIEC_GLOBAL_REG_HLK_INT_STATUS_LEN            9
#define HIPCIEC_GLOBAL_REG_HLK_INT_STATUS_OFFSET         3
#define HIPCIEC_GLOBAL_REG_APB_TIMEOUT_INT_STATUS_LEN    1
#define HIPCIEC_GLOBAL_REG_APB_TIMEOUT_INT_STATUS_OFFSET 2
#define HIPCIEC_GLOBAL_REG_PORT_INT_STATUS_8_15_LEN      1
#define HIPCIEC_GLOBAL_REG_PORT_INT_STATUS_8_15_OFFSET   1
#define HIPCIEC_GLOBAL_REG_PORT_INT_STATUS_0_7_LEN       1
#define HIPCIEC_GLOBAL_REG_PORT_INT_STATUS_0_7_OFFSET    0

#define HIPCIEC_GLOBAL_REG_DFX_CORECLK_EXIST_LEN     16
#define HIPCIEC_GLOBAL_REG_DFX_CORECLK_EXIST_OFFSET  16
#define HIPCIEC_GLOBAL_REG_DFX_CORECLK_DETECT_LEN    16
#define HIPCIEC_GLOBAL_REG_DFX_CORECLK_DETECT_OFFSET 0

#define HIPCIEC_GLOBAL_REG_ECO_REGIF_LEN    16
#define HIPCIEC_GLOBAL_REG_ECO_REGIF_OFFSET 0

#define HIPCIEC_GLOBAL_REG_PORT7_LINK_MODE_LEN    3
#define HIPCIEC_GLOBAL_REG_PORT7_LINK_MODE_OFFSET 28
#define HIPCIEC_GLOBAL_REG_PORT6_LINK_MODE_LEN    3
#define HIPCIEC_GLOBAL_REG_PORT6_LINK_MODE_OFFSET 24
#define HIPCIEC_GLOBAL_REG_PORT5_LINK_MODE_LEN    3
#define HIPCIEC_GLOBAL_REG_PORT5_LINK_MODE_OFFSET 20
#define HIPCIEC_GLOBAL_REG_PORT4_LINK_MODE_LEN    3
#define HIPCIEC_GLOBAL_REG_PORT4_LINK_MODE_OFFSET 16
#define HIPCIEC_GLOBAL_REG_PORT3_LINK_MODE_LEN    3
#define HIPCIEC_GLOBAL_REG_PORT3_LINK_MODE_OFFSET 12
#define HIPCIEC_GLOBAL_REG_PORT2_LINK_MODE_LEN    3
#define HIPCIEC_GLOBAL_REG_PORT2_LINK_MODE_OFFSET 8
#define HIPCIEC_GLOBAL_REG_PORT1_LINK_MODE_LEN    3
#define HIPCIEC_GLOBAL_REG_PORT1_LINK_MODE_OFFSET 4
#define HIPCIEC_GLOBAL_REG_PORT0_LINK_MODE_LEN    3
#define HIPCIEC_GLOBAL_REG_PORT0_LINK_MODE_OFFSET 0

#define HIPCIEC_GLOBAL_REG_PORT15_LINK_MODE_LEN    3
#define HIPCIEC_GLOBAL_REG_PORT15_LINK_MODE_OFFSET 28
#define HIPCIEC_GLOBAL_REG_PORT14_LINK_MODE_LEN    3
#define HIPCIEC_GLOBAL_REG_PORT14_LINK_MODE_OFFSET 24
#define HIPCIEC_GLOBAL_REG_PORT13_LINK_MODE_LEN    3
#define HIPCIEC_GLOBAL_REG_PORT13_LINK_MODE_OFFSET 20
#define HIPCIEC_GLOBAL_REG_PORT12_LINK_MODE_LEN    3
#define HIPCIEC_GLOBAL_REG_PORT12_LINK_MODE_OFFSET 16
#define HIPCIEC_GLOBAL_REG_PORT11_LINK_MODE_LEN    3
#define HIPCIEC_GLOBAL_REG_PORT11_LINK_MODE_OFFSET 12
#define HIPCIEC_GLOBAL_REG_PORT10_LINK_MODE_LEN    3
#define HIPCIEC_GLOBAL_REG_PORT10_LINK_MODE_OFFSET 8
#define HIPCIEC_GLOBAL_REG_PORT9_LINK_MODE_LEN     3
#define HIPCIEC_GLOBAL_REG_PORT9_LINK_MODE_OFFSET  4
#define HIPCIEC_GLOBAL_REG_PORT8_LINK_MODE_LEN     3
#define HIPCIEC_GLOBAL_REG_PORT8_LINK_MODE_OFFSET  0

#define HIPCIEC_GLOBAL_REG_PCS_SFT_RST_LEN         1
#define HIPCIEC_GLOBAL_REG_PCS_SFT_RST_OFFSET      16
#define HIPCIEC_GLOBAL_REG_PCS_LANE_SFT_RST_LEN    16
#define HIPCIEC_GLOBAL_REG_PCS_LANE_SFT_RST_OFFSET 0

#define HIPCIEC_GLOBAL_REG_CFG_RST_DLY_CNT_LEN    16
#define HIPCIEC_GLOBAL_REG_CFG_RST_DLY_CNT_OFFSET 0

#define HIPCIEC_GLOBAL_REG_PORT_BUSI_INT_RO_0_7_LEN    24
#define HIPCIEC_GLOBAL_REG_PORT_BUSI_INT_RO_0_7_OFFSET 0

#define HIPCIEC_GLOBAL_REG_PORT_BUSI_INT_RO_8_15_LEN    24
#define HIPCIEC_GLOBAL_REG_PORT_BUSI_INT_RO_8_15_OFFSET 0

#define HIPCIEC_GLOBAL_REG_CORE_BUSI_INT_SET_LEN    2
#define HIPCIEC_GLOBAL_REG_CORE_BUSI_INT_SET_OFFSET 0

#define HIPCIEC_GLOBAL_REG_CORE_BUSI_INT_MASK_LEN    2
#define HIPCIEC_GLOBAL_REG_CORE_BUSI_INT_MASK_OFFSET 0

#define HIPCIEC_GLOBAL_REG_CORE_BUSI_INT_RO_LEN    2
#define HIPCIEC_GLOBAL_REG_CORE_BUSI_INT_RO_OFFSET 0

#define HIPCIEC_GLOBAL_REG_PORT_BUSI_INT_STATUS_8_15_LEN    1
#define HIPCIEC_GLOBAL_REG_PORT_BUSI_INT_STATUS_8_15_OFFSET 1
#define HIPCIEC_GLOBAL_REG_PORT_BUSI_INT_STATUS_0_7_LEN     1
#define HIPCIEC_GLOBAL_REG_PORT_BUSI_INT_STATUS_0_7_OFFSET  0

#endif // __HIPCIEC_GLOBAL_REG_REG_OFFSET_FIELD_H__
